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PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
PD78P0308
8-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
The PD78P0308 is a member of the PD780308 Subseries of the 78K/0 Series, in which the on-chip mask ROM of the PD780308 is replaced with a one-time PROM or EPROM. Because this device can be programmed by users, it is ideally suited for system evaluation, small-scale and multiple-device production, and early development and time-to-market. Caution The PD78P0308KL-T does not maintain planned reliability when used in your systems' massproduced products. manufacture. The details of functions are described in the user's manuals. Be sure to read the following manuals before designing. Please use only experimentally or for evaluation purposes during trial
PD780308, 780308Y Subseries User's Manual
78K/0 Series User's Manual Instructions
: U11377E : U12326E
FEATURES
* Pin-compatible with mask ROM version (except VPP pin) * Internal PROM: 60 KbytesNote * PD78P0308KL-T * PD78P0308GC, PD78P0308GF * Internal high-speed RAM * Internal expansion RAM * LCD display RAM * Supply voltage : Reprogrammable (ideally suited for system evaluation) : One-time programmable (ideally suited for small-scale production) : 1024 bytes : 1024 bytes : 40 x 4 bits : VDD = 2.7 to 5.5 V
* Corresponding to QTOPTM Microcontrollers (under planning) Note The internal PROM capacity can be changed by setting the memory size switching register (IMS). Remarks 1. QTOP microcontroller is a general term for microcontrollers that incorporate one-time PROM and are totally supported by NEC's programming service (from programming to marking, screening, and verification). 2. Refer to 1. DIFFERENCES BETWEEN THE PD78P0308 AND MASK ROM VERSIONS for the difference between the PROM and mask ROM versions.
In this document, the term PROM is used in parts common to one-time PROM versions and EPROM versions.
The information in this document is subject to change without notice. Document No. U11776EJ1V0DS00 (1st edition) Date Published December 1997 N Printed in Japan
The mark
shows major revised points
(c)
1996
PD78P0308
ORDERING INFORMATION
Part Number Package 100-pin plastic LQFP (fine pitch) (14 x 14 mm) 100-pin plastic QFP (14 x 20 mm) 100-pin ceramic WQFN (14 x 20 mm) Internal ROM One-Time PROM One-Time PROM EPROM Quality Grades Standard Standard Not applicable (for evaluation)
PD78P0308GC-8EU PD78P0308GF-3BA PD78P0308KL-T
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document number C11531E) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
2
Preliminary Data Sheet
PD78P0308
78K/0 SERIES DEVELOPMENT
The following shows the 78K/0 Series product lineup. Subseries names are shown inside frames.
Products in mass production Products under development Y subseries products are compatible with I2C bus specification. Control 100-pin 100-pin 100-pin 100-pin 80-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 42/44-pin
PD780058 PD78058F PD78054 PD780034 PD780024 PD78014H PD78018F PD78014 PD780001 PD78002 PD78083 PD78018FY PD78014Y PD78002Y PD78075B PD78078 PD78070A PD78078Y PD78070AY PD780018AY PD780058YNote PD78058FY PD78054Y PD780034Y PD780024Y
EMI-noise reduced version of the PD78078 A timer was added to the PD78054 and the external interface was enhanced. ROM-less version of the PD78078 Serial I/O of the PD78078Y was enhanced and a limited number of functions is provided. Serial I/O of the PD78054 was enhanced and EMI noise was reduced. EMI-noise reduced version of the PD78054 UART and D/A converter were added to the PD78014 and the I/O was enhanced. A/D converter of the PD780024 was enhanced. Serial I/O of the PD78018F was enhanced. EMI-noise reduced version of the PD78018F
Low-voltage (1.8 V) operation version of the PD78014 with several ROM and RAM capacities available
A/D converter and 16-bit timer were added to the PD78002. A/D converter was added to the PD78002. Basic subseries for control On-chip UART, capable of operating at low voltage (1.8 V)
Inverter control 64-pin 64-pin 64-pin 78K/0 Series
PD780988 PD780964 PD780924
Inverter control function, timer, and serial I/O of the PD780964 were enhanced and ROM/RAM capacities are expanded. A/D converter of the PD780924 was enhanced. On-chip inverter control circuit and UART. EMI noise was reduced.
FIPTM drive 100-pin 100-pin 80-pin 80-pin
PD780208 PD780228 PD78044H PD78044F
The I/O and FIP C/D of the PD78044F were enhanced, Display output total: 53 The I/O and FIP C/D of the PD78044H were enhanced, Display output total: 48 N-ch open-drain I/O was added to the PD78044F, Display output total: 34 Basic subseries for driving FIP, Display output total: 34
LCD drive 100-pin 100-pin 100-pin
PD780308 PD78064B PD78064 PD78064Y PD780308Y
Serial I/O of the PD78064 was enhanced and ROM/RAM capacities are expanded. EMI-noise reduced version of the PD78064 Basic subseries for driving LCD, on-chip UART
IEBusTM supported 80-pin 80-pin
PD78098B PD78098
EMI-noise reduced version of the PD78098 IEBus controller was added to the PD78054
Meter control 80-pin
PD780973
On-chip controller/driver for driving automobile meter
Note Under planning
Preliminary Data Sheet
3
PD78P0308
The following lists the main functional differences between subseries products.
Function Subseries Name Control ROM Capacity 32K-40K 48K-60K - 24K-60K 48K-60K 16K-60K 8K-32K - 8 ch 8 ch - - 3 ch (UART: 1 ch, time division 3-wire: 1 ch) 2 ch 8K-60K 8K-32K 8K 8K-16K - - 1 ch - 8K-60K 8K-32K 3 ch Note1
Note2
8-bit 10-bit 8-bit 8-bit 16-bit Watch WDT A/D A/D D/A 4 ch 1 ch 1 ch 1 ch 8 ch -
Timer
Serial Interface
I/O 88
VDD MIN. Value 1.8 V
External Expansion A
PD78075B PD78078 PD78070A PD780058 PD78058F PD78054 PD780034 PD780024 PD78014H PD78018F PD78014 PD780001 PD78002 PD78083
2 ch 3 ch (UART: 1 ch)
61 2 ch 3 ch (time division UART: 1 ch) 68 3 ch (UART: 1 ch) 69
2.7 V 1.8 V 2.7 V 2.0 V
51
1.8 V
53
2.7 V 1 ch - 8 ch 1 ch - 8 ch - 1 ch (UART: 1 ch) 3 ch (UART: 2 ch) 2 ch (UART: 2 ch) 8 ch - - - 2 ch 1 ch 74 72 68 2 ch 2 ch 1 ch 1 ch 1 ch 8 ch - - 3 ch (time division UART: 1 ch) 57 2 ch (UART: 1 ch) 2.0 V N/A 2.7 V 4.5 V 2.7 V N/A 39 53 33 47 1.8 V 2.7 V 4.0 V N/A A N/A A
Inverter control
PD780988 PD780964 PD780924
-
FIP drive
PD780208 PD780228 PD78044H PD78044F
32K-60K 48K-60K 32K-48K 16K-40K 48K-60K 32K 16K-32K 40K-60K 32K-60K 24K-32K
2 ch 1 ch 1 ch 1 ch 8 ch 3 ch - -
2 ch 1 ch 1 ch
LCD drive
PD780308 PD78064B PD78064
IEBus PD78098B supported PD78098 Meter
2 ch 1 ch 1 ch 1 ch 8 ch
-
2 ch 3 ch (UART: 1 ch)
69
2.7 V
A
PD780973
3 ch 1 ch 1 ch 1 ch 5 ch
-
-
2 ch (UART: 1 ch)
56
4.5 V
N/A
Notes 1. 2. Remark
16-bit timer: 2 channels 10-bit timer: 1 channel 10-bit timer: 1 channel A : Available
N/A : Not available
4
Preliminary Data Sheet
PD78P0308
FUNCTION DESCRIPTION
Item Internal memory * PROM: 60 KbytesNote * RAM High-speed RAM: 1024 bytes Expansion RAM: 1024 bytes LCD display RAM: 40 x 4 bits General register Minimum instruction execution time When main system clock is selected When subsystem clock is selected Instruction set * 16-bit operation * Multiply/divide (8 bits x 8 bits, 16 bits / 8 bits) * Bit manipulate (set, reset, test, Boolean operation) * BCD adjust, etc. I/O ports (Segment signal output pin included) A/D converter LCD Controller/driver Total * CMOS input * CMOS input/output * 8-bit resolution x 8 channels * Supply voltage * Segment signal output * Common signal output * Bias Serial interface : VDD0 = VDD1 = AVREF = 4.0 to 5.5 V : 40 pins maximum : 4 pins maximum : 1/2,1/3 bias convertible : 1 channel : 1 channel : 1 channel : 1 channel : 2 channels : 1 channel : 1 channel : 57 :2 : 55 122 s (@ 32.768-kHz operation) 8 bits x 32 registers (8 bits x 8 registers x 4 banks) Minimum instruction execution time variable function is integrated. 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s/12.8 s (@ 5.0-MHz operation) Function
* 3-wire serial I/O/SBI/2-wire serial I/O mode selectable * 3-wire serial I/O/UART mode selectable * 3-wire serial I/O mode
Timer
* 16-bit timer/event counter * 8-bit timer/event counter * Watch timer * Watchdog timer
Timer output Clock output
3 pins (14-bit PWM output enable: 1 pin) 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, and 5.0 MHz (@ 5.0-MHz operation with main system clock) 32.768 kHz (@ 32.768-kHz operation with subsystem clock)
Buzzer output
1.2 kHz, 2.4 kHz, 4.9 kHz, and 9.8 kHz (@ 5.0-MHz operation with main system clock)
Note Internal PROM capacity can be changed with the memory size switching register (IMS).
Preliminary Data Sheet
5
PD78P0308
Item Vectored interrupt sources Test input Supply voltage Package Maskable Non-maskable Software Internal: 13, External: 6 Internal: 1 1 Internal: 1, External: 1 VDD = 2.7 to 5.5 V * 100-pin plastic LQFP (fine pitch) (14 x 14 mm) * 100-pin plastic QFP (14 x 20 mm) * 100-pin ceramic WQFN (14 x 20 mm) Function
6
Preliminary Data Sheet
PD78P0308
PIN CONFIGURATIONS (Top View) (1) Normal operating mode * 100-pin plastic LQFP (fine pitch) (14 x 14 mm)
PD78P0308GC-8EU
P110/S13 P05/INTP5 P04/INTP4 P03/INTP3 P02/INTP2 P01/INTP1/TI01 P00/INTP0/TI00 RESET XT2 XT1/P07 VDD1 X1 X2 VPP P72/SCK2/ASCK P71/SO2/TXD
P11/ANI1 P12/ANI2 P13/ANI3 P14/ANI4 P15/ANI5 P16/ANI6 P17/ANI7 VDD0 AVREF P100 P101 VSS1 P102 P103 P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P37 COM0 COM1 COM2
1 2 3 4 5 6 7 8 9
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P10/ANI0 AVSS P117 P116 P115 P114/RXD P113/TXD P112/SCK3 P111/SO3
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
P70/SI2/RxD P27/SCK0 P26/SO0/SB1 P25/SI0/SB0 P80/S39 P81/S38 P82/S37 P83/S36 P84/S35 P85/S34 P86/S33 P87/S32 P90/S31 P91/S30 P92/S29 P93/S28 P94/S27 P95/S26 P96/S25 P97/S24 S23 S22 S21 S20 S19
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
COM3 BIAS VLC0 VLC1
VLC2 VSS0 S0 S1 S2 S3 S4 S5 S6 S7 S8
S11 S12 S13 S14 S15 S16 S17
S9 S10
Cautions 1. 2.
Connect VPP pin directly to VSS0 or VSS1. Connect AVSS pin to VSS0.
Remark When this device is used in applications where noise generated from the microcontroller should be reduced, VDD0 and VDD1 should be powered separately, and noise reduction measures should be implemented, such as connecting VSS0 and VSS1 to separate ground lines.
S18
Preliminary Data Sheet
7
PD78P0308
* 100-pin plastic QFP (14 x 20 mm)
PD78P0308GF-3BA
* 100-pin ceramic WQFN (14 x 20 mm)
PD78P0308KL-T
P25/SI0/SB0
P80/S39
P81/S38
P82/S37
P83/S36
P84/S35
P85/S34
P86/S33
P87/S32
P90/S31
P91/S30
P92/S29
P93/S28
P94/S27
P95/S26
P96/S25
P97/S24
S23
P26/SO0/SB1 P27/SCK0 P70/SI2/RXD P71/SO2/TXD P72/SCK2/ASCK VPP X2 X1 VDD1 XT1/P07 XT2 RESET P00/INTP0/TI00 P01/INTP1/TI01 P02/INTP2 P03/INTP3 P04/INTP4 P05/INTP5 P110/SI3 P111/SO3 P112/SCK3 P113/TXD P114/RXD P115 P116 P117 AVSS P10/ANI0 P11/ANI1 P12/ANI2
1 2 3 4 5 6 7 8 9
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
S22 S21
S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 VSS0 VLC2 VLC1 VLC0 BIAS COM3 COM2 COM1 COM0
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
P15/ANI5
AVREF
P13/ANI3
P14/ANI4
P16/ANI6
P17/ANI7
P101
P102
P103
P30/TO0
P31/TO1 P32/TO2
P33/TI1
P34/TI2
P35/PCL
Cautions 1. 2.
Connect VPP pin directly to VSS0 or VSS1. Connect AVSS pin to VSS0.
Remark When this device is used in applications where noise generated from the microcontroller should be reduced, VDD0 and VDD1 should be powered separately, and noise reduction measures should be implemented, such as connecting VSS0 and VSS1 to separate ground lines.
8
Preliminary Data Sheet
P36/BUZ
VDD0
P100
VSS1
P37
PD78P0308
ANI0-ANI7 ASCK AVREF AVSS BIAS BUZ COM0-COM3 INTP0-INTP5 P00-P05, P07 P10-P17 P25-P27 P30-P37 P70-P72 P80-P87 P90-P97 P100-P103 P110-P117 : Analog Input : Asynchronous Serial Clock : Analog Reference Voltage : Analog Ground : LCD Power Supply Bias Control : Buzzer Clock : Common Output : Interrupt from Peripherals : Port 0 : Port 1 : Port 2 : Port 3 : Port 7 : Port 8 : Port 9 : Port 10 : Port 11 PCL RESET RxD S0-S39 SB0, SB1 SCK0, SCK2, SCK3 SI0, SI2, SI3 SO0, SO2, SO3 TI00, TI01, TI1,TI2 TO0-TO2 TxD VDD0, VDD1 VLC0-VLC2 VPP VSS0, VSS1 X1, X2 XT1, XT2 : Programmable Clock : Reset : Receive Data : Segment Output : Serial Bus : Serial Clock : Serial Input : Serial Output : Timer Input : Timer Output : Transmit Data : Power Supply : LCD Power Supply : Programming Power Supply : Ground : Crystal (Main System Clock) : Crystal (Subsystem Clock)
Preliminary Data Sheet
9
PD78P0308
(2) PROM programming mode * 100-pin plastic LQFP (fine pitch) (14 x 14 mm)
PD78P0308GC-8EU
RESET Open (L)
VDD (L) Open
PGM (L) A9
(L)
(L)
1 2 3
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
CE OE
VPP
(L)
(L) A0 A1 A2 A3 A4 A5 A6 A7 A8 A16 A10 A11 A12 A13 A14 A15
(L)
4 5 6 7
VDD VDD (L) VSS (L) D0 D1 D2 D3 D4 D5 D6 D7 (L)
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
(L)
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Cautions 1. 2. 3. 4.
(L): VSS: Open:
Independently connect to VSS via a pull-down resistor. Connect to GND. Leave open.
RESET: Set to low level.
10
Preliminary Data Sheet
(L)
PD78P0308
* 100-pin plastic QFP (14 x 20 mm)
PD78P0308GF-3BA
* 100-pin ceramic WQFN
(L) A0 A1 A2 A3 A4 A5 A6 A7 A8 A16 A10 A11 A12 A13 A14 A15 (L)
79 78
77
PD78P0308KL-T
1 2
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80
(L)
3 4 5
76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
VPP Open (L) VDD (L) Open
6 7 8 9 10 11 12 13 14 15 16
RESET A9 (L)
PGM (L) OE CE
(L)
17 18 19 20 21 22 23 24 25
(L)
26 27 28 29 30
VDD VDD
(L)
(L)
VSS
Cautions 1. 2. 3. 4. A0 to A16 CE D0 to D7 OE PGM
(L): VSS: Open:
Independently connect to VSS via a pull-down resistor. Connect to GND. Leave open. RESET VDD VPP VSS : Reset : Power Supply : Programming Power Supply : Ground
RESET: Set to low level.
: Address Bus : Chip Enable : Data Bus : Output Enable : Program
(L)
D0 D1 D2 D3 D4 D5 D6 D7
Preliminary Data Sheet
11
PD78P0308
BLOCK DIAGRAM
TO0/P30 TI00/INTP0/P00 TI01/INTP1/P01
16-bit TIMER/ EVENT COUNTER
P00 PORT0 P01-P05 P07
TO1/P31 TI1/P33 TO2/P32 TI2/P34
8-bit TIMER/EVENT COUNTER 1
PORT1
8-bit TIMER/EVENT COUNTER 2
P10-P17
PORT2
WATCHDOG TIMER
P25-P27
PORT3
WATCH TIMER
P30-P37
PORT7 SI0/SB0/P25 SO0/SB1/P26 SCK0/P27
SERIAL INTERFACE 0
P70-P72
PORT8
P80-P87
SI2/RxD/P70 SO2/TxD/P71 RxD/P114 TxD/P113 SCK2/ASCK/P72
SERIAL INTERFACE 2
78K/0 CPU CORE
PROM (60K Bytes)
PORT9
P90-P97
PORT10
P100-P103
SI3/P110 SO3/P111 SCK3/P112
PORT11
SERIAL INTERFACE 3
P110-P117
S0-S23 ANI0/P10ANI7/P17 AVSS AVREF
RAM (2048 Bytes) A/D CONVERTER LCD CONTROLLER/ DRIVER
S24/P97S31/P90 S32/P87S39/P80 COM0-COM3 VLC0-VLC2
INTP0/P00INTP5/P05
INTERRUPT CONTROL
BIAS fLCD RESET
SYSTEM CONTROL
BUZ/P36
BUZZER OUTPUT
X1 X2 XT1/P07 XT2
PCL/P35
CLOCK OUTPUT CONTROL
VDD0, VDD1 VSS0, VSS1
VPP
12
Preliminary Data Sheet
PD78P0308
CONTENTS
1. DIFFERENCES BETWEEN THE PD78P0308 AND MASK ROM VERSIONS ........................... 14 2. PIN FUNCTIONS .............................................................................................................................. 15
2.1 2.2 2.3 Pins in Normal Operating Mode .............................................................................................................. 15 Pins in PROM Programming Mode ......................................................................................................... 18 Pin Input/Output Circuits and Recommended Connection of Unused Pins .......................................... 19
3. MEMORY SIZE SWITCHING REGISTER (IMS) ............................................................................. 23 4. INTERNAL EXPANSION RAM SIZE SWITCHING REGISTER (IXS) ........................................... 24 5. PROM PROGRAMMING .................................................................................................................. 25
5.1 5.2 5.3 Operating Modes ...................................................................................................................................... 25 PROM Write Procedure ........................................................................................................................... 27 PROM Read Procedure ........................................................................................................................... 31
6. PROGRAM ERASURE (PD78P0308KL-T ONLY) ....................................................................... 32 7. OPAQUE FILM ON ERASURE WINDOW (PD78P0308KL-T ONLY) ......................................... 32 8. ONE-TIME PROM VERSION SCREENING .................................................................................... 32 9. ELECTRICAL SPECIFICATIONS ................................................................................................... 33 10. PACKAGE DRAWINGS ................................................................................................................... 57 APPENDIX A. DEVELOPMENT TOOLS ............................................................................................ 60 APPENDIX B. RELATED DOCUMENTS ............................................................................................ 66
Preliminary Data Sheet
13
PD78P0308
1. DIFFERENCES BETWEEN THE PD78P0308 AND MASK ROM VERSIONS
The PD78P0308 is a single-chip microcontroller with an on-chip one-time PROM or with an on-chip EPROM, which has program write, erasure, and rewrite capability. It is possible to make all the functions except for PROM specification, and mask option of LCD drive power supply split resistor, the same as those of mask ROM versions by setting the memory size switching register (IMS). Difference between the PROM version (PD78P0308) and mask ROM versions (PD780306, 780308) are shown in Table 1-1. Table 1-1. Differences between the PD78P0308 and Mask ROM Versions
Item Internal ROM configuration Internal ROM capacity
PD78P0308
One-time PROM/EPROM 60 Kbytes
Mask ROM Versions Mask ROM
PD780306: PD780308:
48 Kbytes 60 Kbytes
Internal ROM capacity change by the memory size switching register (IMS) IC pin VPP pin Mask options of LCD drive power supply split resistor Electrical specifications, recommended soldering conditions
Possible
Note
Impossible
No Yes None
Yes No Available
Refer to data sheet of the individual product.
Note The internal PROM capacity is set to 60 Kbytes by RESET input. Caution There are differences in noise immunity and noise radiation between the PROM and mask ROM versions. When pre-producing an application set with the PROM version and then mass-producing it with the mask ROM version, be sure to conduct sufficient evaluations for the set using consumer samples (not engineering samples) of the mask ROM version.
14
Preliminary Data Sheet
PD78P0308
2. PIN FUNCTIONS
2.1 Pins in Normal Operating Mode
(1) Port pins (1/2)
Pin Name P00 P01 P02 P03 P04 P05 P07Note 1 P10-P17 Input Input/output Port 1 8-bit input/output port Input/output is specifiable bit-wise. When used as the input port, on-chip pull-up resistor connection can be specified by means of software. P25 P26 P27 P30 P31 P32 P33 P34 P35 P36 P37 Input/output Input/output Port 2 3-bit input/output port Input/output is specifiable bit-wise. When used as the input port, on-chip pull-up resistor connection can be specified by means of software. Port 3 8-bit input/output port Input/output is specifiable bit-wise. When used as the input port, on-chip pull-up resistor connection can be specified by means of software. Input SO0/SB1 SCK0 TO0 TO1 TO2 TI1 TI2 PCL BUZ --
Note 2
Input/Output Input Input/output Port 0 7-bit input/output port
Function Input only Input/output is specifiable bit-wise. When used as the input port, on-chip pull-up resistor connection can be specified by means of software. Input only
After Reset Input Input
Alternate Function INTP0/TI00 INTP1/TI01 INTP2 INTP3 INTP4 INTP5
Input Input
XT1 ANI0-ANI7
Input
SI0/SB0
Notes 1. 2.
When P07/XT1 pins are used as the input ports, set bit 6 (FRC) of the processor clock control register (PCC) to 1, and be sure not to use the feedback resistor of the subsystem clock oscillator. When P10/ANI0-P17/ANI7 pins are used as the analog inputs for the A/D converter, shift port 1 to input mode. The on-chip pull-up resistor is automatically disabled.
Preliminary Data Sheet
15
PD78P0308
(1) Port pins (2/2)
Pin Name P70 P71 P72 P80-P87
Input/Output Input/output Port 7 3-bit input/output port
Function
After Reset Input
Alternate Function SI2/RXD SO2/TXD SCK2/ASCK
Input/output is specifiable bit-wise. When used as the input port, on-chip pull-up resistor connection can be specified by means of software. Input/output Port 8 8-bit input/output port Input/output is specifiable bit-wise. When used as the input port, on-chip pull-up resistor connection can be specified by means of software. Input/output port/segment signal output function is specifiable in 2-bit units by the LCD display control register (LCDC). Input
S39-S32
P90-P97
Input/output
Port 9 8-bit input/output port Input/output is specifiable bit-wise. When used as the input port, on-chip pull-up resistor connection can be specified by means of software. Input/output port/segment signal output function is specifiable in 2-bit units by the LCD display control register (LCDC).
Input
S31-S24
P100-P103
Input/output
Port 10 4-bit input/output port Input/output is specifiable bit-wise. When used as the input port, on-chip pull-up resistor connection can be specified by means of software. It is possible to directly drive LEDs.
Input
--
P110 P111 P112 P113 P114 P115-P117
Input/output
Port 11 8-bit input/output port Input/output is specifiable bit-wise. When used as the input port, on-chip pull-up resistor connection can be specified by means of software. Falling edge detection is possible.
Input
SI3 SO3 SCK3 TXD RXD --
16
Preliminary Data Sheet
PD78P0308
(2) Non-port pins (1/2)
Pin Name INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 SI0 SI2 SI3 SO0 SO2 SO3 SB0 SB1 SCK0 SCK2 SCK3 RxD TxD ASCK TI00 TI01 TI1 TI2 TO0 TO1 TO2 PCL BUZ S0-S23 S24-S31 S32-S39 COM0-COM3 Output VLC0-VLC2 BIAS -- -- LCD controller/driver common signal output. LCD drive voltage. LCD drive power supply. Output -- -- Output Output Output Output Input Output Input Input Asynchronous serial interface serial data input. Asynchronous serial interface serial data output. Asynchronous serial interface serial clock input. External count clock input to 16-bit timer (TM0). Capture trigger signal input to capture register (CR00). External count clock input to 8-bit timer (TM1). External count clock input to 8-bit timer (TM2). 16-bit timer (TM0) output (also used for 14-bit PWM output). 8-bit timer (TM1) output. 8-bit timer (TM2) output. Clock output (for main system clock, subsystem clock trimming). Buzzer output. LCD controller/driver segment signal output. Input Output Input P36 -- P97-P90 P87-P80 -- -- -- Input Input Input Input Input Input Input/output Serial interface serial clock input/output. Input Input/output Serial interface serial data input/output. Input Output Serial interface serial data output. Input Input Serial interface serial data input. Input Input/Output Input Function External interrupt request input for which the active edge (rising edge, falling edge, or both rising and falling edges) can be specified. After Reset Input Alternate Function P00/TI00 P01/TI01 P02 P03 P04 P05 P25/SB0 P70/RxD P110 P26/SB1 P71/TxD P111 P25/SI0 P26/SO0 P27 P72/ASCK P112 P70/SI2, P114 P71/SO2, P113 P72/SCK2 P00/INTP0 P01/INTP1 P33 P34 P30 P31 P32 P35
Preliminary Data Sheet
17
PD78P0308
(2) Non-port pins (2/2)
Pin Name ANI0-ANI7 AVREF AVSS RESET X1 X2 XT1 XT2 VDD0 VSS0 VDD1 VSS1 VPP Input -- -- -- -- -- -- Input Input -- Input/Output Input Input -- Function A/D converter analog input. A/D converter reference voltage input (also used for analog input). A/D converter ground potential. Set to the same potential as VSS0. System reset input. Crystal resonator connection for main system clock oscillation. Crystal resonator connection for subsystem clock oscillation. Positive power supply for ports. Ground potential for ports. Positive power supply (except for ports and analog). Ground potential (except for ports and analog). High voltage application in program write/verify mode. Connect directly to VSS0 or VSS1 in normal operating mode. Input -- -- -- -- -- -- -- -- -- -- P07 -- -- -- -- -- -- -- -- -- -- After Reset Input -- Alternate Function P10-P17 --
2.2
Pins in PROM Programming Mode
Input/Output Input PROM programming mode setting. When +5 V or +12.5 V is applied to the VPP pin and a low-level signal is applied to the RESET pin, this chip is set in the PROM programming mode. Function
Pin Name RESET
VPP A0-A16 D0-D7 CE OE PGM VDD VSS
Input Input Input/output Input Input Input -- --
PROM programming mode setting and high voltage application during program write/verification. Address bus. Data bus. PROM enable input/program pulse input. Read strobe input to PROM. Program/program inhibit input in PROM programming mode. Positive power supply. Ground potential.
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Preliminary Data Sheet
PD78P0308
2.3 Pin Input/Output Circuits and Recommended Connection of Unused Pins
Types of input/output circuits of the pins and recommended connection of unused pins are shown in Table 2-1. For the configuration of each type of input/output circuit, see Figure 2-1. Table 2-1. Type of Input/Output Circuit of Each Pin (1/2)
Pin Name P00/INTP0/TI00 P01/INTP1/TI01 P02/INTP2 P03/INTP3 P04/INTP4 P05/INTP5 P07/XT1 P10/ANI0-P17/ANI7 P25/SI0/SB0 P26/SO0/SB1 P27/SCK0 P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P37 P70/SI2/RXD P71/SO2/TXD P72/SCK2/ASCK P80/S39-P87/S32 P90/S31-P97/S24 P100-P103 P110/SI3 P111/SO3 P112/SCK3 P113/TXD P114/RXD P115-P117 S0-S23 COM0-COM3 17-B 18-A Output Leave open. 5-H 8-C Independently connect to VDD0 via a resistor. 8-C 5-H 8-C 17-C 5-H 8-C 5-H 16 11-B 10-B Input Input/output Connect to VDD0. Independently connect to VDD0 or VSS0 via a resistor. Input/Output Circuit Type 2 8-C Input Input/output Connect to VSS0. Independently connect to VSS0 via a resistor. Input/Output Recommended Connection for Unused Pins
Preliminary Data Sheet
19
PD78P0308
Table 2-1. Type of Input/Output Circuit of Each Pin (2/2)
Pin Name VLC0-VLC2 BIAS RESET XT2 AVREF AVSS VPP
Input/Output Circuit Type -- 2 16 --
Input/Output -- Input -- --
Recommended Connection for Unused Pins Leave open. -- Leave open. Connect to VSS0. Connect directly to VSS0 or VSS1.
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Preliminary Data Sheet
PD78P0308
Figure 2-1. List of Pin Input/Output Circuits (1/2)
Type 2
Type 10-B
VDD0
pullup enable IN data VDD0 P-ch
P-ch
IN/OUT Schmitt-triggered input with hysteresis characteristics open drain output disable N-ch VSS0
Type 5-H pullup enable VDD0 data
VDD0
Type 11-B pullup enable data
VDD0
P-ch
P-ch VDD0 P-ch IN/OUT
P-ch IN/OUT output disable P-ch N-ch VSS0 Comparator + - VSS0 N-ch
output disable
input enable
AVSS N-ch VREF (threshold voltage) input enable VDD0 Type 16 feedback cut-off P-ch
Type 8-C
pullup enable VDD0 data P-ch
P-ch
IN/OUT output disable N-ch VSS0 XT1 XT2
Preliminary Data Sheet
21
PD78P0308
Figure 2-1. List of Pin Input/Output Circuits (2/2)
Type 17-B VLC0 VLC1 N-ch P-ch SEG data P-ch VLC2 N-ch VSS1 N-ch OUT
Type 17-C VDD0 P-ch pullup enable VDD0 data P-ch IN/OUT output disable VSS0 input enable N-ch P-ch
Type 18-A VLC0 VLC0 VLC1 P-ch N-ch P-ch N-ch SEG data OUT VLC2 P-ch VLC2 N-ch VSS1 VSS1 N-ch P-ch N-ch P-ch VLC1 N-ch P-ch
COM data
N-ch
P-ch
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Preliminary Data Sheet
PD78P0308
3. MEMORY SIZE SWITCHING REGISTER (IMS)
This is a register to disable use of part of internal memories by software. By setting this memory size switching register (IMS), it is possible to get the same memory map as that of the mask ROM versions with a different internal memory (ROM) capacity. IMS is set with an 8-bit memory manipulation instruction. RESET input sets IMS to CFH. Figure 3-1. Memory Size Switching Register Format
Symbol IMS 7 RAM2 6 RAM1 5 RAM0 4 0 3 ROM3 2 ROM2 1 ROM1 0 ROM0 Address FFF0H After Reset CFH R/W R/W
ROM3 ROM2 ROM1 ROM0 Internal ROM Capacity Selection 1 1 1 1 0 1 0 1 48 Kbytes 60 Kbytes Setting prohibited
Other than above
RAM2 RAM1 RAM0
Internal High-Speed RAM Capacity Selection 1024 bytes Setting prohibited
1
1
0
Other than above
Table 3-1 shows the setting values of IMS that make the memory mapping the same as that of the mask ROM version. Table 3-1. Memory Size Switching Register Setting Values
Target Mask ROM Versions IMS Setting Value CCH CFH
PD780306 PD780308
Preliminary Data Sheet
23
PD78P0308
4. INTERNAL EXPANSION RAM SIZE SWITCHING REGISTER (IXS)
This register is used to set the internal expansion RAM capacity by software. By setting this internal expansion RAM size switching register (IXS), it is possible to get the same memory map as that of the mask ROM versions with a different internal expansion RAM capacity. IXS is set with an 8-bit memory manipulation instruction. RESET input sets IXS to 0AH. Figure 4-1. Internal Expansion RAM Size Switching Register Format
Symbol IXS 7 0 6 0 5 0 4 0 3 IXRAM3 2 IXRAM2 1 IXRAM1 0 IXRAM0 Address FFF4H After Reset 0AH R/W W
IXRAM3 1
IXRAM2 0
IXRAM1 1
IXRAM0 0
Internal Expansion RAM Capacity Selection 1024 bytes Setting prohibited
Other than above
Table 4-1 shows the setting values of IXS that make the memory mapping the same as that of the mask ROM versions. Table 4-1. Internal Expansion RAM Size Switching Register Setting Values
Target Mask ROM Versions IXS Setting Value 0AH
PD780306 PD780308
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Preliminary Data Sheet
PD78P0308
5. PROM PROGRAMMING
The PD78P0308 has an on-chip 60-Kbyte PROM as a program memory. For programming, set the PROM programming mode with the VPP and RESET pins. For the connection of unused pins, refer to "PIN CONFIGURATIONS (2) PROM programming mode." Caution Programs must be written in addresses 0000H to EFFFH (The last address EFFFH must be specified). They cannot be written by a PROM programmer that cannot specify the write address. 5.1 Operating Modes
When +5 V or +12.5 V is applied to the VPP pin and a low-level signal is applied to the RESET pin, the PROM programming mode is set. This mode will become the operating mode as shown in Table 5-1 when the CE, OE and PGM pins are set as shown. Further, when the read mode is set, it is possible to read the contents of the PROM.
Table 5-1. Operating Modes of PROM Programming
Pin Operating Mode Page data latch Page write Byte write Program verify Program inhibit L +12.5 V +6.5 V H H L L x x Read Output disable Standby +5 V +5 V L L H L H H L H L L H x H L L H H L H x x Data output High-impedance High-impedance Data input High-impedance Data input Data output High-impedance RESET VPP VDD CE OE PGM D0-D7
x : L or H
Preliminary Data Sheet
25
PD78P0308
(1) Read mode Read mode is set if CE = L, OE = L is set. (2) Output disable mode Data output becomes high-impedance, and is in the output disable mode, if OE = H is set. Therefore, it allows data to be read from any device by controlling the OE pin, if multiple PD78P0308s are connected to the data bus. (3) Standby mode Standby mode is set if CE = H is set. In this mode, data outputs become high-impedance irrespective of the OE status. (4) Page data latch mode Page data latch mode is set if CE = H, PGM = H, OE = L are set at the beginning of page write mode. In this mode, 1 page 4-byte data is latched in an internal address/data latch circuit. (5) Page write mode After 1 page 4 bytes of addresses and data are latched in the page data latch mode, a page write is executed by applying a 0.1-ms program pulse (active low) to the PGM pin with CE = H, OE = H. Then, program verification can be performed, if CE = L, OE = L are set. If programming is not performed by a one-time program pulse, X times (X 10) write and verification operations should be executed repeatedly. (6) Byte write mode Byte write is executed when a 0.1-ms program pulse (active low) is applied to the PGM pin with CE = L, OE = H. Then, program verification can be performed if OE = L is set. If programming is not performed by a one-time program pulse, X times (X 10) write and verification operations should be executed repeatedly. (7) Program verify mode Program verify mode is set if CE = L, PGM = H, OE = L are set. In this mode, check if a write operation is performed correctly after the write. (8) Program inhibit mode Program inhibit mode is used when the OE pin, VPP pin, and D0-D7 pins of multiple PD78P0308s are connected in parallel and a write is performed to one of those devices. When a write operation is performed, the page write mode or byte write mode described above is used. At this time, a write is not performed to a device whose PGM pin is driven high.
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Preliminary Data Sheet
PD78P0308
5.2 PROM Write Procedure Figure 5-1. Page Program Mode Flow Chart
Start Address = G VDD = 6.5 V, VPP = 12.5 V
X=0 Latch Address = Address + 1 Latch Address = Address + 1 Latch Address = Address + 1 Address = Address + 1 Latch No X = 10 ? Yes
X=X+1 0.1-ms program pulse
Verify 4 bytes Pass No Address = N ? Yes
VDD = 4.5 to 5.5 V, VPP = VDD
Fail
Pass
Verify all bytes All Pass Write end
Fail
Defective product
G = Start address N = Program last address
Preliminary Data Sheet
27
PD78P0308
Figure 5-2. Page Program Mode Timing
Page Data Latch
Page Program
Program Verify
A2-A16
A0, A1
Hi-Z D0-D7 Data Input VPP VPP VDD VDD + 1.5 VDD VDD VIH CE VIL Data Output
VIH PGM VIL VIH OE VIL
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Preliminary Data Sheet
PD78P0308
Figure 5-3. Byte Program Mode Flow Chart
Start Address = G VDD = 6.5 V, VPP = 12.5 V
X=0
X=X+1 0.1-ms program pulse Address = Address + 1 Fail Verify Pass No Address = N ? Yes
VDD = 4.5 to 5.5 V, VPP = VDD
No X = 10 ? Yes
Pass
Verify all bytes All Pass Write end
Fail
Defective product
G = Start address N = Program last address
Preliminary Data Sheet
29
PD78P0308
Figure 5-4. Byte Program Mode Timing
Program
Program Verify
A0-A16
D0-D7
Hi-Z Data Input Data Output
VPP VPP VDD
VDD
VDD + 1.5 VDD VIH
CE VIL VIH PGM VIL VIH OE VIL
Cautions 1. 2. 3.
VDD should be applied before VPP, and cut after VPP. VPP should not exceed +13.5 V including overshoot. Disconnection during application of 12.5 V to VPP may have an adverse effect on reliability.
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Preliminary Data Sheet
PD78P0308
5.3 PROM Read Procedure
The contents of PROM are readable to the external data bus (D0-D7) according to the read procedure shown below. (1) Fix the RESET pin at low level, supply +5 V to the VPP pin, and connect all other unused pins as shown in "PIN CONFIGURATIONS (2) PROM programming mode". (2) Supply +5 V to the VDD and VPP pins. (3) Input address of data to be read into the A0-A16 pins. (4) Read mode (5) Output data to D0-D7 pins. The timings of the above steps (2) to (5) are shown in Figure 5-5. Figure 5-5. PROM Read Timings
A0-A16
Address Input
CE (Input)
OE (Input)
D0-D7
Hi-Z
Data Output
Hi-Z
Preliminary Data Sheet
31
PD78P0308
6. PROGRAM ERASURE (PD78P0308YKL-T ONLY)
The PD78P0308KL-T is capable of erasing (FFH) the data written in a program memory and rewriting. To erase the programmed data, expose the erasure window to light having a wavelength shorter than about 400 nm. Normally, irradiate ultraviolet rays of 254-nm wavelength. The amount of exposure required to completely erase the programmed data is as follows: * UV intensity x erasing time : 30 W * s/cm2 or more
* Erasure time: 40 min. or more (When a UV lamp of 12 mW/cm2 is used. However, a longer time may be needed because of deterioration in performance of the UV lamp, soiled erasure window, etc.) When erasing the contents of data, set up the UV lamp within 2.5 cm from the erasure window. Further, if a filter is provided for a UV lamp, irradiate the ultraviolet rays after removing the filter.
7. OPAQUE FILM ON ERASURE WINDOW (PD78P0308KL-T ONLY)
To protect from unintentional erasure by rays other than that of the lamp for erasing EPROM contents, or to protect internal circuit other than EPROM from misoperating by rays, cover the erasure window with an opaque film when EPROM contents erasure is not performed.
8. ONE-TIME PROM VERSION SCREENING
The one-time PROM version (PD78P0308GC-8EU and 78P0308GF-3BA) cannot be tested completely by NEC before it is shipped, because of its structure. It is recommended to perform screening to verify PROM after writing necessary data and performing high-temperature storage under the condition below.
Storage Temperature 125C Storage Time 24 hours
NEC offers for an additional fee service from one-time PROM writing to marking, screening, and verify for products designated as "QTOP microcontroller". This additional fee service is being planned for PD78P0308. Please contact an NEC sales representative for details.
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Preliminary Data Sheet
PD78P0308
9. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (TA = 25C)
Parameter Supply voltage Symbol VDD VPP AVREF AVSS Input voltage VI1 P00-P05, P07, P10-P17, P25-P27, P30-P37, P70-P72, P80-P87, P90-P97, P100-P103, P110-P117, X1, X2, XT2, RESET VI2 Output Voltage Analog input voltage Output current, high VO VAN IOH P10-P17 1 pin Total for P01-P05, P10-P17, P25-P27, P70-P72, P110-P117 Total for P30-P37, P80-P87, P90-P97, P100-P117 Output current, low IOL 1 pin Peak value r.m.s. value Total for P01-P05, P10-P17, P110-P117 Total for P30-P37, P100-P103 Peak value r.m.s. value Peak value r.m.s. value Total for P25-P27, P70-P72, P80-P87, P90-P97
Operating ambient temperature
Test Conditions
Ratings -0.3 to +7.0 -0.3 to +13.5 -0.3 to VDD + 0.3 -0.3 to +0.3 -0.3 to VDD + 0.3
Unit V V V V V
A9
PROM Programing mode
-0.3 to +13.5 -0.3 to VDD + 0.3
V V V mA mA
Analog input pin
AVSS - 0.3 to AVREF + 0.3 -10 -15
-15 30 15
Note
mA mA mA mA mA mA mA mA mA C C
60 40
Note
140 100
Note
Peak value r.m.s. value
50 20
Note
TA Tstg
-40 to +85 -65 to +150
Storage temperature
Note
The root mean square (r.m.s.) value should be calculated as follows: [r.m.s. value] = [Peak value] x Duty The product quality may be damaged even if a value of only one of the above parameters exceeds the absolute maximum rating or any value exceeds the absolute maximum rating for an instant. That is, the absolute maximum rating is a rating value which may cause a product to be damaged physically. The absolute maximum rating values must therefore be observed in using the product.
Caution
Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. CAPACITANCE (TA = 25C, VDD = VSS = 0 V)
Parameter Input capacitance Output capacitance I/O capacitance Symbol CIN COUT CIO Test Conditions f = 1 MHz Unmeasured pins returned to 0 V. MIN. TYP. MAX. 15 15 15 Unit pF pF pF
Preliminary Data Sheet
33
PD78P0308
MAIN SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (TA = -40 to +85C, VDD = 2.7 to 5.5 V)
Recommended circuit VPP X2 R1 C2 C1 X1
Resonator Ceramic resonator
Parameter Oscillation frequency (fX)Note 1 Oscillation stabilization timeNote 2 Oscillation frequency (fX)Note 1 Oscillation stabilization timeNote 2 X1 input frequency (fX)Note 1 X1 input high-/low-level width (tXH , tXL)
Test conditions VDD = Oscillation voltage range After VDD reaches oscillation voltage range MIN.
MIN. 1.0
TYP.
MAX. 5.0
Unit MHz
4
ms
Crystal resonator
VPP X2 R1 C2
X1
1.0
5.0
MHz
C1
VDD = 4.5 to 5.5 V
10 30 1.0 5.0
ms
External clock
X2 X1
MHz
PD74HCU04
85
500
ns
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after reset or STOP mode release. Cautions 1. When using the main system clock oscillator, wiring in the area enclosed with the broken line should be carried out as follows to avoid an adverse effect from wiring capacitance. * Wiring should be as short as possible. * Wiring should not cross other signal lines. * Wiring should not be placed close to a varying high current. * The potential of the oscillator capacitor ground should be the same as VSS. * Do not ground it to the ground pattern in which a high current flows. * Do not fetch a signal from the oscillator. 2. If the main system clock oscillator is operated by the subsystem clock when the main system clock is stopped, reswitching to the main system clock should be performed after the oscillation stabilization time has been obtained by the program.
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Preliminary Data Sheet
PD78P0308
SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS (TA = -40 to +85C, VDD = 2.7 to 5.5 V)
Resonator Crystal resonator Parameter Oscillation frequency (fXT)Note 1 Test Conditions MIN. TYP. MAX. Unit
Recommended Circuit
VPP XT1
XT2 R2
32
32.768
35
kHz
C3
C4
Oscillation stabilization timeNote 2
VDD = 4.5 to 5.5 V
1.2
2 10
s
External clock
XT1 XT2
XT1 input frequency (fXT)Note 1
32
100
kHz
XT1 input high-/low-level width (tXTH/tXTL)
5
15
s
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after VDD has reached the minimum oscillation voltage range. Cautions 1. When using the subsystem clock oscillator, wiring in the area enclosed with the broken line should be carried out as follows to avoid an adverse effect from wiring capacitance. * Wiring should be as short as possible. * Wiring should not cross other signal lines. * Wiring should not be placed close to a varying high current. * The potential of the oscillator capacitor ground should be the same as VSS. * Do not ground it to the ground pattern in which a high current flows. * Do not fetch a signal from the oscillator. 2. The subsystem clock oscillator is designed as a low-amplification circuit to provide low consumption current, causing misoperation due to noise more frequently than the main system clock oscillator. Special care should therefore be taken regarding the wiring method when the subsystem clock is used.
Preliminary Data Sheet
35
PD78P0308
DC CHARACTERISTICS (TA = -40 to +85C, VDD = 2.7 to 5.5 V)
Parameter Input voltage, high Symbol VIH1 Test Conditions P10-P17, P30-P32, P35-P37, P80-P87, P90-P97, P100-P103 VIH2 P00-P05, P25-P27, P33, P34, P70-P72, P110-P117, RESET VIH3 VIH4 X1, X2 XT1/P07, XT2 4.5 VDD 5.5 V 2.7 VDD < 4.5 V Input voltage, low VIL1 P10-P17, P30-P32, P35-P37, P80-P87, P90-P97, P100-P103 VIL2 P00-P05, P25-P27, P33, P34, P70-P72, P110-P117, RESET VIL3 VIL4 X1, X2 XT1/P07, XT2 4.5 VDD 5.5 V 2.7 VDD < 4.5 V Output voltage, high Output voltage, low P01-P05, P10-P17, P25-P27, P30-P37, P70-P72, P80-P87, P90-P97, P110-P117 VOL2 SB0, SB1, SCK0 VDD = 4.5 to 5.5 V, open-drain, pulled up (R = 1 k) VOL3 IOL = 400 A 0.5 V 0.2VDD V VOL1 VOH VDD = 4.5 to 5.5 V IOH = -1 mA IOH = -100 A P100-P103 VDD = 4.5 to 5.5 V, IOL = 15 mA VDD = 4.5 to 5.5 V, IOL = 1.6 mA 0.4 V 0 0 0 VDD - 1.0 VDD - 0.5 0.4 0.4 0.2VDD 0.1VDD VDD VDD 2.0 V V V V V V 0 0.2VDD V VDD - 0.5 0.8VDD 0.9VDD 0 VDD VDD VDD 0.3VDD V V V V 0.8VDD VDD V MIN. 0.7VDD TYP. MAX. VDD Unit V
Remark
Unless otherwise specified, the characteristics of alternate-function pins are the same as the those of port pins.
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Preliminary Data Sheet
PD78P0308
DC CHARACTERISTICS (TA = -40 to +85C, VDD = 2.7 to 5.5 V)
Parameter Input leakage current, high Symbol ILIH1 VIN = VDD Test Conditions P00-P05, P10-P17, P25-P27, P30-P37, P70-P72, P80-P87, P90-P97, P100-P103, P110-P117 X1, X2, XT1/P07, XT2 VIN = 0 V P00-P05, P10-P17, P25-P27, P30-P37, P70-P72, P80-P87, P90-P97, P100-P103, P110-P117 X1, X2, XT1/P07, XT2 VOUT = VDD VOUT = 0 V VIN = 0 V P01-P05, P10-P17, P25P27, P30-P37, P70-P72, P80-P87, P90-P97, P100-P103, P110-P117 VDD = 5.0 V 10%Note 5 VDD = 3.0 V 10%Note 6 10%Note 5 15 40 MIN. TYP. MAX. 3 Unit
A
ILIH2 Input leakage current, low ILIL1
20 -3
A A
ILIH2 Output leakage current, high Output leakage current, low Software pull-up resistor ILOH ILOL R
-20 3 -3 90
A A A
k
Supply currentNote 1
IDD1
5.00-MHz crystal oscillation (fXX = 2.5 MHz)Note 2 operating mode
5 0.7 9 1 1.4 500 1.6 650 135 95 25 5 1 0.5 0.1 0.05
15 2.1 27 3 4.2 1500 4.8 1950 270 190 55 15 30 10 30 10
mA mA mA mA mA
5.00-MHz crystal oscillation (fXX = VDD = 5.0 V 5.0 MHz)Note 3 operating mode VDD = 3.0 V 10%Note 6 IDD2 5.00-MHz crystal oscillation (fXX = 2.5 MHz)Note 2 HALT mode 5.00-MHz crystal oscillation (fXX = 5.0 MHz)Note 3 HALT mode IDD3 32.768-kHz crystal oscillation operating IDD4 modeNote 4 VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 5.0 V 10% VDD = 3.0 V 10%
A
mA
A A A A A A A A A
32.768-kHz crystal oscillation HALT modeNote 4
IDD5
XT1 = VDD STOP mode When feedback resistor is connected
IDD6
XT1 = VDD VDD = 5.0 V 10% STOP mode When feedback resistor is disconnected VDD = 3.0 V 10%
Notes 1. Current flowing into VDD pin. Not including the current flowing into A/D converter, on-chip pull-up resistors, or LCD split resistors. 2. Main system clock fXX = fX/2 operation (when oscillation mode selection register (OSMS) is set to 00H) 3. Main system clock fXX = fX operation (when OSMS is set to 01H) 4. When the main system clock is stopped. 5. High-speed mode operation (when processor clock control register (PCC) is set to 00H) 6. Low-speed mode operation (when PCC is set to 04H) Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as the those of port pins.
Preliminary Data Sheet
37
PD78P0308
LCD CONTROLLER/DRIVER CHARACTERISTICS (AT NORMAL OPERATION) (1) Static Display Mode (TA = -10 to +85C, VDD = 2.7 to 5.5 V)
Parameter LCD drive voltage LCD output voltage deviationNote (common) LCD output voltage deviationNote (segment) Symbol VLCD VODC VODS IO = 5 A IO = 1 A Test Conditions VLCD0 = VLCD MIN. 2.7 0 0 TYP. MAX. VDD 0.2 0.2 Unit V V V
Note
The voltage deviation is the difference between the output voltage and the corresponding ideal value of the segment or common output (VLCDn; n = 0, 1, 2).
(2) 1/3 Bias Method (TA = -10 to +85C, VDD = 2.7 to 5.5 V)
Parameter LCD drive voltage LCD output voltage deviationNote (common) LCD output voltage deviationNote (segment) Symbol VLCD VODC VODS IO = 5 A IO = 1 A Test Conditions MIN. 2.7 0 0 TYP. MAX. VDD 0.2 0.2 Unit V V V
VLCD0 = VLCD VLCD1 = VLCD x 2/3 VLCD2 = VLCD x 1/3
Note
The voltage deviation is the difference between the output voltage and the corresponding ideal value of the segment or common output (VLCDn; n = 0, 1, 2).
(3) 1/2 Bias Method (TA = -10 to +85C, VDD = 2.7 to 5.5 V)
Parameter LCD drive voltage LCD output voltage deviationNote (common) LCD output voltage deviationNote (segment) Symbol VLCD VODC VODS IO = 5 A IO = 1 A Test Conditions MIN. 2.7 0 0 TYP. MAX. VDD 0.2 0.2 Unit V V V
VLCD0 = VLCD VLCD1 = VLCD x 1/2 VLCD2 = VLCD1
Note
The voltage deviation is the difference between the output voltage and the corresponding ideal value of the segment or common output (VLCDn; n = 0, 1, 2).
Caution Characteristics at low-voltage operation are undecided.
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Preliminary Data Sheet
PD78P0308
AC CHARACTERISTICS (1) Basic Operation (TA = -40 to +85C, VDD = 2.7 to 5.5 V)
Parameter Cycle time (Min. instruction execution time)
Symbol TCY
Test Conditions Operating on main system clock (fXX = 2.5 Operating on main system clock 4.5 VDD 5.5 V (fXX = 5.0 MHz)Note 2 2.7 VDD < 4.5 V Operating on subsystem clock 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V MHz)Note 1
MIN. 0.8 0.4 0.8 40Note 3 2/fsam+0.1Note 4 2/fsam+0.2Note 4 10
TYP.
MAX. 64 32 32
Unit
s s s s s s s
122
125
TI00 input high/ low-level width TI01 input high/ low-level width TI1, TI2 input frequency TI1, TI2 input high/low-level width Interrupt request input high/lowlevel width RESET low-level width
tTIH00, tTIL00 tTIH01, tTIL01 fTI1
VDD = 4.5 to 5.5 V
0 0
4 275
MHz kHz ns
tTIH1, tTIL1 tINTH, tINTL
VDD = 4.5 to 5.5 V
100 1.8 4.5 V VDD 5.5 V 2/fsam+0.1Note 4 2.7 V VDD < 4.5 V 2/fsam+0.2Note 4 10 10
s s s s s
INTP0
INTP1-INTP5, P110-P117 tRSL
Notes 1. Main system clock fXX = fX/2 operation (when oscillation mode selection register (OSMS) is set to 00H) 2. Main system clock fXX = fX operation (when OSMS is set to 01H) 3. This is the value when the external clock is used. The value is 114 s (min.) when the crystal resonator is used. 4. In combination with bits 0 (SCS0) and 1 (SCS1) of the sampling clock select register (SCS), selection of fsam is possible between fXX/2N+1, fXX/32, fXX/64, and fXX/128 (when N = 0 to 4).
Preliminary Data Sheet
39
PD78P0308
TCY vs VDD (At main system clock fXX = fX/2 operation)
60
TCY vs VDD (At main system clock fXX = fX operation)
60 32
Cycle Time TCY [ s]
10 Guaranteed Operation Range
Cycle Time TCY [ s]
10 Guaranteed Operation Range
2.0
2.0
1.0 0.8 0.4
1.0 0.8 0.4
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Supply Voltage VDD [V]
Supply Voltage VDD [V]
40
Preliminary Data Sheet
PD78P0308
(2) Serial Interface (TA = -40 to +85C, VDD = 2.7 to 5.5 V) (a) Serial interface channel 0 (i) 3-wire serial I/O mode (SCK0... Internal clock output)
Symbol tKCY1 Test Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V SCK0 high/low-level width tKH1, tKL1 tSIK1 tKSI1 tKSO1 C = 100 pFNote VDD = 4.5 to 5.5 V 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V SI0 hold time (from SCK0) SO0 output delay time from SCK0 MIN. 800 1600 tKCY1/2 - 50 tKCY1/2 - 100 100 150 400 300 TYP. MAX. Unit ns ns ns ns ns ns ns ns
Parameter SCK0 cycle time
SI0 setup time (to SCK0)
Note
C is the load capacitance of the SCK0 and SO0 output lines. (ii) 3-wire serial I/O mode (SCK0... External clock input)
Parameter Symbol tKCY2 Test Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V MIN. 800 1600 400 800 100 400 C = 100 pF
Note
TYP.
MAX.
Unit ns ns ns ns ns ns
SCK0 cycle time
SCK0 high/low-level width SI0 setup time (to SCK0) SI0 hold time (from SCK0) SO0 output delay time from SCK0 SCK0 rise, fall time
tKH2, tKL2 tSIK2 tKSI2 tKSO2
300
ns
tR2, tF2
1000
ns
Note
C is the load capacitance of the SO0 output line.
Preliminary Data Sheet
41
PD78P0308
(iii) SBI mode (SCK0... Internal clock output)
Parameter SCK0 cycle time Symbol tKCY3 Test Conditions VDD = 4.5 to 5.5 V MIN. 800 3200 SCK0 high-/low-level width tKH3, tKL3 SB0, SB1 setup time (to SCK0) SB0, SB1 hold time (from SCK0) SB0, SB1 output delay time from SCK0 SB0, SB1 from SCK0 SCK0 from SB0, SB1 SB0, SB1 high-level width SB0, SB1 low-level width tKSB tSBK tSBH tSBL tKSO3 R = 1 k, C = 100 pFNote VDD = 4.5 to 5.5 V 0 0 tKCY3 tKCY3 tKCY3 tKCY3 250 1000 ns ns ns ns ns ns tKSI3 tSIK3 VDD = 4.5 to 5.5 V VDD = 4.5 to 5.5 V tKCY3/2 - 50 tKCY3/2 - 150 100 300 tKCY3/2 TYP. MAX. Unit ns ns ns ns ns ns ns
Note
R and C are the load resistance and load capacitance of the SCK0, SB0, and SB1 output lines.
(iv) SBI mode (SCK0... External clock input)
Parameter SCK0 cycle time Symbol tKCY4 Test Conditions VDD = 4.5 to 5.5 V MIN. 800 3200 SCK0 high-/low-level width tKH4, tKL4 SB0, SB1 setup time (to SCK0) SB0, SB1 hold time (from SCK0) SB0, SB1 output delay time from SCK0 SB0, SB1 from SCK0 SCK0 from SB0, SB1 SB0, SB1 high-level width SB0, SB1 low-level width SCK0 rising/falling time tKSB tSBK tSBH tSBL tR4, tF4 tKSO4 R = 1 k, C = 100 pF
Note
TYP.
MAX.
Unit ns ns ns ns ns ns ns
VDD = 4.5 to 5.5 V
400 1600
tSIK4
VDD = 4.5 to 5.5 V
100 300
tKSI4
tKCY4/2
VDD = 4.5 to 5.5 V
0 0 tKCY4 tKCY4 tKCY4 tKCY4
300 1000
ns ns ns ns ns ns
1000
ns
Note
R and C are the load resistance and load capacitance of the SB0 and SB1 output lines.
42
Preliminary Data Sheet
PD78P0308
(v) 2-wire serial I/O mode (SCK0... Internal clock output)
Parameter SCK0 cycle time SCK0 high-level width SCK0 low-level width Symbol tKCY5 tKH5 tKL5 R = 1 k, C = 100 pFNote VDD = 4.5 to 5.5 V 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V tKSI5 Test Conditions MIN. 1600 tKCY5/2 - 160 tKCY5/2 - 50 tKCY5/2 - 100 SB0, SB1 setup time (to SCK0) SB0, SB1 hold time (from SCK0) SB0, SB1 output delay time from SCK0 tSIK5 300 350 600 TYP. MAX. Unit ns ns ns ns ns ns ns
tKSO5
300
ns
Note
R and C are the load resistance and load capacitance of the SCK0, SB0, and SB1 output lines. (vi) 2-wire serial I/O mode (SCK0... External clock input)
Parameter Symbol tKCY6 tKH6 tKL6 tSIK6 Test Conditions MIN. 1600 650 800 100 TYP. MAX. Unit ns ns ns ns
SCK0 cycle time SCK0 high-level width SCK0 low-level width SB0, SB1 setup time (to SCK0) SB0, SB1 hold time (from SCK0) SB0, SB1 output delay time from SCK0 SCK0 rise, fall time
tKSI6
tKCY6/2
ns
tKSO6
R = 1 k, VDD = 4.5 to 5.5 V C = 100 pFNote
0 0
300 500 1000
ns ns ns
tR6, tF6
Note
R and C are the load resistance and load capacitance of the SB0 and SB1 output lines.
Preliminary Data Sheet
43
PD78P0308
(b) Serial interface channel 2 (i) 3-wire serial I/O mode (SCK2... Internal clock output)
Symbol tKCY7 Test Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V SCK2 high/low-level width tKH7, tKL7 SI2 setup time (to SCK2) tSIK7 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V SI2 hold time (from SCK2) SO2 output delay time from SCK2 tKSI7 tKSO7 C = 100 pFNote VDD = 4.5 to 5.5 V MIN. 800 1600 tKCY7/2 - 50 tKCY7/2 - 100 100 150 400 300 TYP. MAX. Unit ns ns ns ns ns ns ns ns
Parameter SCK2 cycle time
Note
C is the load capacitance of the SCK2 and SO2 output lines. (ii) 3-wire serial I/O mode (SCK2... External clock input)
Parameter Symbol tKCY8 Test Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V MIN. 800 1600 400 800 100 400 C = 100 pFNote 300 1000 TYP. MAX. Unit ns ns ns ns ns ns ns ns
SCK2 cycle time
SCK2 high/low-level width
tKH8, tKL8
SI2 setup time (to SCK2) SI2 hold time (from SCK2) SO2 output delay time from SCK2 SCK2 rise, fall time
tSIK8 tKSI8 tKSO8 tR8, tF8
Note
C is the load capacitance of the SO2 output line.
44
Preliminary Data Sheet
PD78P0308
(iii) UART mode (Dedicated baud rate generator output)
Parameter Transfer rate Symbol Test Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V MIN. TYP. MAX. 78125 39063 Unit bps bps
(iv) UART mode (External clock input)
Parameter ASCK cycle time Symbol tKCY9 Test Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V ASCK high/low-level width Transfer rate tKH9, tKL9 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V ASCK rise, fall time tR9, tF9 MIN. 800 1600 400 800 39063 19531 1000 TYP. MAX. Unit ns ns ns ns bps bps ns
(c) Serial interface channel 3 Undecided
Preliminary Data Sheet
45
PD78P0308
AC Timing Test Point (Excluding X1, XT1 Inputs)
0.8VDD 0.2VDD
Test Points
0.8VDD 0.2VDD
Clock Timing
1/fX
tXL
tXH VDD-0.5 V 0.4 V
X1 Input
1/fXT
tXTL XT1 Input
tXTH VIH4 (MIN.) VIL4 (MAX.)
TI Timing
tTIL00, tTIL01
tTIH00, tTIH01
TI00, TI01
1/fTI1
tTIL1
tTIH1
TI1, TI2
46
Preliminary Data Sheet
PD78P0308
Serial Transfer Timing 3-wire serial I/O mode:
tKCYm
tKLm tRn SCK0, SCK2 tSIKm tKSIm
tKHm tFn
SI0, SI2 tKSOm
Input data
SO0, SO2
Output data
m = 1, 2, 7, 8 n = 2, 8
SBI mode (bus release signal transfer):
tKCY3, 4 tKL3, 4 tR4 SCK0 tSIK3, 4 tKH3, 4 tF4
tKSB SB0, SB1
tSBL
tSBH
tSBK
tKSI3, 4
tKSO3, 4
SBI mode (command signal transfer):
tKCY3, 4 tKL3, 4 tR4 SCK0 tSIK3, 4 tKH3, 4 tF4
tKSB SB0, SB1
tSBK
tKSI3, 4
tKSO3, 4
Preliminary Data Sheet
47
PD78P0308
2-wire serial I/O mode:
tKCY5, 6 tKL5, 6 tR6 SCK0 tSIK5, 6 tKSO5, 6 tKSI5, 6 tKH5, 6 tF6
SB0, SB1
UART mode:
tKCY9 tKL9 tR9 ASCK tKH9 tF9
A/D Converter (TA = -40 to +85C, AVDD = VDD = AVREF = 4.0 to 5.5 V, AVSS = VSS = 0 V)
Parameter Resolution Overall errorNote 1 Conversion time Sampling time Analog input voltage Reference voltage AVREF-AVSS resistance AVREF current tCONV tSAMP VIAN AVREF RREF AIREF When not operating A/D conversion When operating A/D conversionNote 2 When not operating A/D conversionNote 3 19.1 12/fXX AVSS 4.0 4 14 2.0 0.5 4.0 1.5 AVREF AVDD Symbol Test Conditions MIN. 8 TYP. 8 MAX. 8 0.6 200 Unit bit %
s s
V V k mA mA
Notes 1. Quantization error (1/2 LSB) is not included. This is expressed in proportion to the full-scale value. 2. Indicates current flowing to AVREF pin when the CS bit of the A/D converter mode register (ADM) is 1. 3. Indicates current flowing to AVREF pin when the CS bit of ADM is 0.
48
Preliminary Data Sheet
PD78P0308
DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (TA = -40 to +85C)
Parameter Data retention supply voltage Data retention power supply current IDDDR VDDDR = 1.8 V Subsystem clock stop and feed-back resistor disconnected. Release signal set time Oscillation stabilization wait time tSREL tWAIT Release by RESET Release by interrupt request 0 217/fx Note 0.1 10 Symbol VDDDR Test Conditions MIN. 1.8 TYP. MAX. 5.5 Unit V
A
s
ms ms
Note In combination with bits 0 to 2 (OSTS0 to OSTS2) of the oscillation stabilization time select register (OSTS), selection of 212/fXX and 214/fXX to 217/fXX is possible. Data Retention Timing (STOP Mode Release by RESET)
Internal Reset Operation HALT Mode STOP Mode Operating Mode
Data Retention Mode
VDD STOP Instruction Execution RESET
VDDDR tSREL
tWAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
HALT Mode STOP Mode Operating Mode
Data Retention Mode
VDD STOP Instruction Execution Standby Release Signal (Interrupt Request)
VDDDR tSREL
tWAIT
Preliminary Data Sheet
49
PD78P0308
Interrupt Request Input Timing
tINTL
tINTH
INTP0-INTP5
RESET Input Timing
tRSL
RESET
50
Preliminary Data Sheet
PD78P0308
PROM PROGRAMMING CHARACTERISTICS DC Characteristics (1) PROM Write Mode (TA = 25 5C, VDD = 6.5 0.25 V, VPP = 12.5 0.3 V)
Parameter Input voltage high Input voltage low Output voltage high Output voltage low Input leakage current VPP supply voltage VDD supply voltage VPP supply current VDD supply current Symbol VIH VIL VOH VOL ILI VPP VDD IPP IDD Symbol VIH VIL VOH VOL ILI VPP VCC IPP ICC PGM = VIL IOH = -1 mA IOL = 1.6 mA 0 VIN VDD -10 12.2 6.25 12.5 6.5
Note
Test Conditions
MIN. 0.7VDD 0 VDD - 1.0
TYP.
MAX. VDD 0.3VDD
Unit V V V
0.4 +10 12.8 6.75 50 50
V
A
V V mA mA
(2) PROM Read Mode (TA = 25 5C, VDD = 5.0 0.5 V, VPP = VDD 0.6 V)
Parameter Input voltage high Input voltage low Output voltage high Symbol VIH VIL VOH1 VOH2 Output voltage low Input leakage current Output leakage current VPP supply voltage VDD supply voltage VPP supply current VDD supply current VOL ILI ILO VPP VDD IPP IDD Symbol VIH VIL VOH1 VOH2 VOL ILI ILO VPP VCC IPP ICCA1 VPP = VDD CE = VIL, VIN = VIH IOH = -1 mA IOH = -100 A IOL = 1.6 mA 0 VIN VDD 0 VOUT VDD, OE = VIH -10 -10 VDD - 0.6 4.5 VDD 5.0
Note
Test Conditions
MIN. 0.7VDD 0 VDD - 1.0 VDD - 0.5
TYP.
MAX. VDD 0.3VDD
Unit V V V V
0.4 +10 +10 VDD + 0.6 5.5 100 50
V
A A
V V
A
mA
Note
Corresponding PD27C1001A symbol.
Preliminary Data Sheet
51
PD78P0308
AC Characteristics (1) PROM Write Mode (a) Page program mode (TA = 25 5C, VDD = 6.5 0.25 V, VPP = 12.5 0.3 V)
Parameter Address setup time (to OE) OE setup time CE setup time (to OE) Input data setup time (to OE) Address hold time (from OE) Symbol tAS tOES tCES tDS tAH tAHL tAHV Input data hold time (from OE) Data output float delay time from OE VPP setup time (to OE) VDD setup time (to OE) Program pulse width Valid data delay time from OE OE pulse width during data latching PGM setup time CE hold time OE hold time tDH tDF tVPS tVDS tPW tOE tLW tPGMS tCEH tOEH Symbol Note tAS tOES tCES tDS tAH tAHL tAHV tDH tDF tVPS tVCS tPW tOE tLW tPGMS tCEH tOEH 1 2 2 2 Test Conditions MIN. 2 2 2 2 2 2 0 2 0 1.0 1.0 0.095 250 0.105 1 250 TYP. MAX. Unit
s s s s s s s s
ns ms ms ms
s s s s s
(b) Byte program mode (TA = 25 5C, VDD = 6.5 0.25 V, VPP = 12.5 0.3 V)
Parameter Address setup time (to PGM) OE setup time CE setup time (to PGM) Input data setup time (to PGM) Address hold time (from OE) Input data hold time (from PGM) Data output float delay time from OE VPP setup time (to PGM) VDD setup time (to PGM) Program pulse width Valid data delay time from OE OE hold time Symbol tAS tOES tCES tDS tAH tDH tDF tVPS tVDS tPW tOE tOEH Symbol Note tAS tOES tCES tDS tAH tDH tDF tVPS tVCS tPW tOE -- 2 Test Conditions MIN. 2 2 2 2 2 2 0 1.0 1.0 0.095 0.105 1 250 TYP. MAX. Unit
s s s s s s
ns ms ms ms
s s
Note
Corresponding PD27C1001A symbol
52
Preliminary Data Sheet
PD78P0308
(2) PROM Read Mode (TA = 25 5C, VDD = 5.0 0.5 V, VPP = VDD 0.6 V)
Parameter Data output delay time from address Data output delay time from CE Data output delay time from OE Data output float delay time from OE Data hold time from address Symbol tACC tCE tOE tDF tOH Symbol Note tACC tCE tOE tDF tOH Test Conditions CE = OE = VIL OE = VIL CE = VIL CE = VIL CE = OE = VIL 0 0 MIN. TYP. MAX. 800 800 200 60 Unit ns ns ns ns ns
Note Corresponding PD27C1001A symbol (3) PROM Programming Mode Setting (TA = 25C, VSS = 0 V)
Parameter PROM programing mode setup time Symbol tSMA Test Conditions MIN. 10 TYP. MAX. Unit
s
Preliminary Data Sheet
53
PD78P0308
PROM Write Mode Timing (Page Program Mode)
Page Data Latch
Page Program
Program Verify
A2 to A16 tAS A0, A1 tDS D0 to D7 Hi-Z tDH Hi-Z tPGMS Data Output tDF Hi-Z tAHL tAHV
tVPS VPP VPP VDD tVDS VDD + 1.5 VDD VDD
Data Input
tOE
tAH
tCES VIH CE VIL VIH PGM VIL tLW VIH OE VIL tOES tPW tCEH
tOEH
54
Preliminary Data Sheet
PD78P0308
PROM Write Mode Timing (Byte Program Mode)
Program Program Verify
A0 to A16 tAS Hi-Z tDS VPP VPP VDD tVPS VDD + 1.5 VDD VDD VIH CE VIL VIH PGM VIL VIH OE VIL tOES tOE tCES tPW tVDS tOEH Hi-Z tDH tDF Hi-Z tAH
D0 to D7
Data Input
Data Output
Cautions 1. VDD should be applied before VPP, and cut after VPP. 2. VPP should not exceed +13.5 V including overshoot. 3. Disconnection during application of 12.5 V to VPP may have an adverse effect on reliability. PROM Read Mode Timing
A0-A16 Effective Address
VIH CE VIL tCE VIH OE VIL tACCNote 1 D0-D7 Hi-Z tOENote 1 tOH Data Output Hi-Z tDFNote 2
Notes 1. If you want to read within the tACC range, make the OE input delay time from the fall of CE the maximum of tACC - tOE. 2. tDF is the time from when either OE or CE first reaches VIH.
Preliminary Data Sheet
55
PD78P0308
PROM Programming Mode Setting Timing
VDD VDD 0
RESET
VDD VPP 0 tSMA
A0-A16
Effective Address
56
Preliminary Data Sheet
PD78P0308
10. PACKAGE DRAWINGS
100 PIN PLASTIC LQFP (FINE PITCH) (14x14)
A B
75 76
51 50
detail of lead end
CD
S Q R
100 1
26 25
F G P H I
M
J K M
N
NOTE Each lead centerline is located within 0.08 mm (0.003 inch) of its true position (T.P.) at maximum material condition.
L
ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 16.000.20 14.000.20 14.000.20 16.000.20 1.00 1.00 0.22 +0.05 -0.04 0.08 0.50 (T.P.) 1.000.20 0.500.20 0.17 +0.03 -0.07 0.08 1.400.05 0.100.05 3 +7 -3 1.60 MAX. INCHES 0.6300.008 0.551 +0.009 -0.008 0.551 +0.009 -0.008 0.6300.008 0.039 0.039 0.0090.002 0.003 0.020 (T.P.) 0.039 +0.009 -0.008 0.020 +0.008 -0.009 0.007 +0.001 -0.003 0.003 0.0550.002 0.0040.002 3 +7 -3 0.063 MAX. S100GC-50-8EU
Preliminary Data Sheet
57
PD78P0308
100PIN PLASTIC QFP (14x20)
A B
80 81
51 50
detail of lead end CD
S Q R
100 1
31 30
F G H I
M
J
P
K M N L
ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 23.60.4 20.00.2 14.00.2 17.60.4 0.8 0.6 0.300.10 0.15 0.65 (T.P.) 1.80.2 0.80.2 0.15 +0.10 -0.05 0.10 2.70.1 0.10.1 55 3.0 MAX. INCHES 0.9290.016 0.795 +0.009 -0.008 0.551 +0.009 -0.008 0.6930.016 0.031 0.024 0.012 +0.004 -0.005 0.006 0.026 (T.P.) 0.071 +0.008 -0.009 0.031 +0.009 -0.008 0.006 +0.004 -0.003 0.004 0.106 +0.005 -0.004 0.0040.004 55 0.119 MAX. P100GF-65-3BA1-3
NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition.
58
Preliminary Data Sheet
PD78P0308
100 PIN CERAMIC WQFN
A B K Q
T 100
D
C
W
U
H
IM J
1 R
E
F
Z
G
X100KW-65A-1 NOTE Each lead centerline is located within 0.06 mm (0.003 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D E F G H I J K Q R S T U W Z MILLIMETERS 20.6 - 0.4 19.0 13.8 14.6 - 0.4 1.94 2.14 3.5 MAX, 0.45 - 0.10 0.06 0.65 1.0 - 0.2 C 0.3 0.875 1.125 R 3.17 12.0 0.75 - 0.2 0.10 INCHES 0.811 - 0.016 0.748 0.543 0.575 - 0.016 0.076 0.084 0.138 MAX. 0.018 +0.004 --0.005 0.003 0.026 0.039 +0.009 --0.008 C 0.012 0.034 0.044 R 0.125 0.472 0.030 +0.008 --0.009 0.004
Preliminary Data Sheet
59
S
PD78P0308
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are provided for system development using the PD78P0308. Also refer to (5) Precautions in Using Development Tools. (1) Language Processing Software
RA78K/0 CC78K/0 DF780308 CC78K/0-L Assembler package common to 78K/0 Series products C compiler package common to 78K/0 Series products Device file common to PD780308 Subseries products (part number: SxxxxDF78064) C compiler library source file common to 78K/0 Series products
(2) PROM Write Tools
PG-1500 PA-78P0308GC PA-78P0308GF PA-78P0308KL-T PG-1500 Controller Control program for the PG-1500 PROM programmer Programmer adapter connected to the PG-1500
(3) Debugging Tools * When using the IE-78K0-NS as an in-circuit emulator
IE-78K0-NSNote IE-70000-MC-PS-B IE-70000-98-IF-CNote IE-70000-CD-IFNote IE-70000-PC-IF-CNote IE-780308-NS-EM1 NP-100GC NP-100GF TGC-100SDW
Note
In-circuit emulator common to 78K/0 Series products Power supply unit for the IE-78K0-NS Interface adapter when a PC-9800 series PC (excluding notebook-type PCs) is used as the host machine PC card and interface cable when a PC-9800 series notebook-type PC is used as the host machine Interface adapter when an IBM PC/ATTM or its compatible is used as the host machine Emulation board common to PD780308 Subseries products Emulation probe for 100-pin plastic LQFP (GC-8EU type) Emulation probe for 100-pin plastic QFP (GF-3BA type) Conversion adapter to connect the NP-100GC with the target system board prepared for mounting a 100-pin plastic LQFP (GC-8EU type)
EV-9200GF-100 ID78K0-NS SM78K0 DF780308
Note
Socket to be mounted on the target system board prepared for 100-pin plastic QFP (GF-3BA type) Integrated debugger for the IE-78K0-NS System simulator common to 78K/0 Series products Device file common to PD780308 Subseries products (part number: SxxxxDF78064)
Note Under development
60
Preliminary Data Sheet
PD78P0308
* When using the IE-78001-R-A as an in-circuit emulator
IE-78001-R-ANote IE-70000-98-IF-B IE-70000-98-IF-C
Note
In-circuit emulator common to 78K/0 Series products Interface adapter when a PC-9800 series PC (excluding notebook-type PCs) is used as the host machine Interface adapter when an IBM PC/ATTM or its compatible is used as the host machine
IE-70000-PC-IF-B IE-70000-PC-IF-CNote IE-78000-R-SV3 IE-780308-NS-EM1 IE-780308-R-EM IE-78K0-R-EX1Note
Note
Interface adapter and cable when an EWS is used as the host machine Emulation board common to PD780308 Subseries products Emulation probe conversion board required when the IE-780308-NS-EM1 is used in the IE-78001-R-A
EP-78064GC-R EP-78064GF-R TGC-100SDW
Emulation probe for 100-pin plastic LQFP (GC-8EU type) Emulation probe for 100-pin plastic QFP (GF-3BA type) Conversion adapter to connect the EP-78064GC-R with the target system board prepared for mounting a 100-pin plastic LQFP (GC-8EU type)
EV-9200GF-100
Socket to be mounted on the target system board prepared for 100-pin plastic QFP (GF-3BA type)
ID78K0 SM78K0 DF780308
Integrated debugger for the IE-78001-R-A System simulator common to 78K/0 Series products Device file common to PD780308 Subseries products (part number: SxxxxDF78064)
Note Under development (4) Real-Time OS
RX78K/0 MX78K0 Real-time OS for 78K/0 Series products OS for 78K/0 Series products
Preliminary Data Sheet
61
PD78P0308
(5) Precautions in Using Development Tools * The package name of the DF780308 is DF78064. * Use the ID78K0-NS, ID78K0, and SM78K0 in combination with the DF780308. * Use the CC78K/0 and RX78K/0 in combination with the RA78K/0 and DF780308. * The NP-100GC and NP-100GF are products of Naitou Densei Machidaseisakusho Co., Ltd. (tel: (044) 8223813). Contact an NEC dealer to purchase these products. * The TGC-100SDW is a product of TOKYO ELETECH Corporation. Contact: Daimaru Kogyo Co., Ltd. Tokyo Electronic Component Department (tel: (03) 3820-7112) Osaka Electronic Component Department (tel: (06) 244-6672) * Please refer to 78K/0 Series Selection Guide (U11126E) for information on the third party development tools. * The following table shows what host machine and OS support each software.
Host machine [OS] Software RA78K/0 CC78K/0 PG-1500 controller ID78K0-NS ID78K0 SM78K0 RX78K/0 MX78K0
Note
PC PC-9800 series [WindowsTM] IBM PC/AT and its compatibles [Windows]
EWS HP9000 series 700TM [HP-UXTM] SPARCstationTM [SunOSTM] NEWSTM (RISC) [NEWS-OSTM]
Note Note Note
Note
Note DOS-based software.
62
Preliminary Data Sheet
PD78P0308
DRAWING OF CONVERSION ADAPTER (TGC-100SDW)
Figure A-1. Drawing of TGC-100SDW (for reference only) (unit: mm)
X C
A B
N
L M T
O X
FED
HIJK
Protrusion height
V
W
PQRS U
G Y e a n m g I j i f h
ITEM A B C D E F G H I J K L M N O P Q R S T U V W X Y Z MILLIMETERS 21.55 0.5x24=12 0.5 0.5x24=12 15.0 21.55 INCHES 0.848 0.020x0.945=0.472 0.020 0.020x0.945=0.472 0.591 0.848 ITEM a b c d e f g h i j k l m n MILLIMETERS 14.45 1.850.25 3.5 2.0 3.9 0.25 INCHES 0.569 0.0730.010 0.138 0.079 0.154 0.010
Z k
d c b
3.55
10.9 13.3 15.7 18.1 13.75 0.5x24=12.0 1.1250.3 1.1250.2 7.5 10.0 11.3 18.1
0.140
0.429 0.524 0.618 0.713 0.541 0.020x0.945=0.472 0.0440.012 0.0440.008 0.295 0.394 0.445 0.713
4.5
16.0 1.1250.3 0~5 5.9 0.8 2.4 2.7
0.177
0.630 0.0440.012 0.000~0.197 0.232 0.031 0.094 0.106 TGC-100SDW-G1E
5.0
5.0 4- 1.3 1.8 C 2.0
0.197
0.197 4- 0.051 0.071 C 0.079
0.9 0.3
0.035 0.012
note: Product of TOKYO ELETECH CORPORATION.
Preliminary Data Sheet
63
PD78P0308
DRAWINGS OF CONVERSION SOCKET (EV-9200GF-100) AND RECOMMENDED FOOTPRINTS
Figure A-2. Drawing of EV-9200GF-100 (for reference only) A B F
R D C S
E
M N
O
K
EV-9200GF-100
1
No.1 pin index
P
G H I EV-9200GF-100-G0E ITEM A B C D E F G H I J K L M N O P Q R S MILLIMETERS 24.6 21 15 18.6 4-C 2 0.8 12.0 22.6 25.3 6.0 16.6 19.3 8.2 8.0 2.5 2.0 0.35 INCHES 0.969 0.827 0.591 0.732 4-C 0.079 0.031 0.472 0.89 0.996 0.236 0.654 0.76 0.323 0.315 0.098 0.079 0.014
2.3 1.5
0.091 0.059
64
Preliminary Data Sheet
Q
L
J
PD78P0308
Figure A-3. Recommended Footprints of EV-9200GF-100 (for reference only)
G
J K
D H F E
L
I
C B A EV-9200GF-100-P1E ITEM A B C D E F G H I J K L Caution MILLIMETERS 26.3 21.6 INCHES 1.035 0.85
0.650.02 x 29=18.850.05 0.026 +0.001 x 1.142=0.742+0.002 -0.002 -0.002 0.650.02 x 19=12.350.05 0.026 +0.001 x 0.748=0.486 +0.003 -0.002 -0.002 15.6 20.3 12 0.05 6 0.05 0.35 0.02 0.614 0.799 0.472 +0.003 -0.002 0.236 +0.003 -0.002 0.014 +0.001 -0.001
2.36 0.03 2.3 1.57 0.03
0.093+0.001 -0.002 0.091 0.062+0.001 -0.002
Dimensions of mount pad for EV-9200 and that for target device (QFP) may be different in some parts. For the recommended mount pad dimensions for QFP, refer to "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL" (C10535E).
Preliminary Data Sheet
65
PD78P0308
APPENDIX B. RELATED DOCUMENTS
Documents Related to Devices
Document Name Document Number English Japanese U11377J U11105J U11776J U12326J U10903J U10904J To be prepared U10182J
PD780308, 780308Y Subseries User's Manual PD780306, 780308 Data Sheet PD78P0308 Data Sheet
78K/0 Series User's Manual Instructions 78K/0 Series Instruction Application Table 78K/0 Series Instruction Set
U11377E U11105E This document U12326E -- -- -- U10182E
PD780308 Subseries Special Function Register Table
78K/0 Series Application Note Basics III
Documents Related to Development Tools (User's Manual)
Document Name Document Number English RA78K0 Assembler Package Operation Assembly Language Structured Assembly Language RA78K Series Structured Assembler Preprocessor CC78K0 C Compiler Operation Language CC78K0 C Compiler Application Note CC78K Series Library Source File PG-1500 PROM Programmer PG-1500 Controller PC-9800 series (MS-DOSTM) based PG-1500 Controller IBM PC series (PC DOSTM) based IE-78K0-NS IE-78001-R-A IE-78K0-R-EX1 IE-780308-NS-EM1 IE-780308-R-EM EP-78064 SM78K0 System Simulator Windows based SM78K Series System Simulator Reference External Parts User's Open Interface Specifications ID78K0-NS Integrated Debugger ID78K0 Integrated Debugger EWS-based ID78K0 Integrated Debugger PC-based ID78K0 Integrated Debugger Windows-based Reference Reference Reference Guide To be prepared -- U11539E U11649E U12900J U11151J U11539J U11649J Programming Know-how U11802E U11801E U11789E EEU-1402 U11517E U11518E EEA-1208 -- U11940E EEU-1291 U10540E To be prepared To be prepared To be prepared To be prepared U11362E EEU-1469 U10181E U10092E Japanese U11802J U11801J U11789J U12323J U11517J U11518J EEA-618 U12322J U11940J EEU-704 EEU-5008 To be prepared To be prepared To be prepared To be prepared U11362J EEU-934 U10181J U10092J
Caution The contents of the above documents are subject to change without prior notice. Be sure to use the latest edition for design, etc.
66
Preliminary Data Sheet
PD78P0308
Documents Related to Embedded Software (User's Manuals)
Document Name Document Number English 78K/0 Series Real-Time OS Basics Installation 78K/0 Series OS MX78K0 Basics U11537E U11536E U12257E Japanese U11537J U11536J U12257J
Others
Document Name Document No. English IC Package Manual Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Guide to Quality Assurance for Semiconductor Devices Microcomputer Product Series Guide MEI-1202 -- -- U11416J C10943X C10535E C11531E C10983E C11892E C10535J C11531J C10983J C11892J Japanese
Caution
The contents of the above documents are subject to change without notice. Be sure to use the latest edition for design, etc.
Preliminary Data Sheet
67
PD78P0308
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
68
Preliminary Data Sheet
PD78P0308
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics (France) S.A. NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583
NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.1.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388
Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951
NEC do Brasil S.A.
Cumbica-Guarulhos-SP, Brasil Tel: 011-6465-6810 Fax: 011-6465-6829
J97. 8
Preliminary Data Sheet
69
PD78P0308
FIP, IEBus, and QTOP are trademarks of NEC Corporation. MS-DOS and Windows are either registered trademarks or a trademarks of Microsoft Corporation in the United States and/or other countries. PC/AT and PC DOS are trademarks of International Business Machines Corporation. HP9000 series 700, and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. SunOS is a trademark of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of Sony Corporation. The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. License not needed The customer must judge the need for license No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.
M4 96.5
: PD78P0308KL-T : PD78P0308GC-8EU, 78P0308GF-3BA

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